Silicon-based complimentary metal-oxide-semiconductor (CMOS) technology entered the nanometer era around the year 2000 when the semiconductor industry began to produce integrated circuits in the 0.13 micrometer technology node. Within this node, the industry incorporated metal-oxide-semiconductor field effect transistors (MOSFETs) with gate lengths of about 70 nanometers. Since that time, gate lengths have continued to decrease. MOSFETs are expected to have gate lengths on the order of only ten nanometers some time before the year 2020.
The key driver behind these trends is economics. Smaller devices take up less space on an integrated circuit and are less expensive to manufacture. For example, the cost to produce a single MOSFET has decreased by seven orders of magnitude during the last 40 years in large part because of the reduction in their size. In addition, smaller devices typically consume less power and have higher performance when compared to larger devices.
One manner in which to produce nano-scale features (i.e., features with minimum lateral dimensions less than about 100 nanometers) on integrated circuits is to try to print them directly using lithography. Conventional optical lithography enhanced with high numerical apertures, retical enhancement techniques, and double exposures may, for example, pattern devices in the 22 nanometers technology node. Nevertheless, the lithographic tools and enhancements required to achieve these dimensions are typically complex and expensive. As a result, there remains a need for methods of precisely forming nano-scale features on integrated circuits that do not depend on directly printing the features using lithography.